1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor structure, and more particularly to a method of manufacturing a package carrier.
2. Description of Related Art
In the fabrication of semiconductors, chip package carrier is one of the most common used package components. The chip package carrier, for example, is a multi-layered circuit board, in which a plurality of circuit layers and a plurality of dielectric layers are alternately stacked. Each of the dielectric layers is disposed between two adjacent circuit layers, and the circuit layers are electrically connected through the plating through hole (PTH) or via. Since a chip package carrier has the advantages of dense wiring, compact assembly and good electrical performance, it is most widely used in the chip package structure.
Typically, the structure of the multi-layered circuit board commonly formed by the build-up method or the laminating method so that it has the features of high wiring density and small pitch. Since the rigidity of the ultra-thin substrate is poor, it is necessary to provide a metal (such as aluminum substrate or copper substrate) as a supporting carrier. Then, mass of gel are coated on the metal, and then the plurality of circuit layers and the plurality of dielectric layer are alternatively arranged on the two opposite surfaces of the metal. Finally, the gel is removed so that the circuit layers and the dielectric layers are separated from the metal to form two multi-layered circuit boards separated from each other. Moreover, as for forming the plating through hole or via in the multi-layered circuit board, after a dielectric layer is formed, a blind via is formed to expose the circuit layer underneath the dielectric layer. Then, by using copper plating method, a copper layer is plated in the blind via and on the dielectric layer to form connecting layers and the plating through hole or via.
Since, conventionally, the metal is provided to be the supporting carrier of the copper foil and the cost of the metal is relatively high, the cost for manufacturing the multi-layered circuit board is high. Also, the mass of gel is used to fix the copper foil on the metal so that it is difficult to remove the gel and the manufacturing yield is hardly improved. Moreover, as for the circuit layer formed by the copper plating method, the thickness uniformity of the copper layer is poor so that when the required thickness of the circuit layer is small, it is necessary to perform the thinning process (such as etching process) to decrease the thickness of the circuit layer. Thus, the number of the process steps for manufacturing the multi-layered circuit board is increased and the manufacturing yield of the multi-layered circuit board is decreased.